The present invention relates to a method for fabricating a nonvolatile memory device, and more particularly, to a method for fabricating a three-dimensional (3D) nonvolatile memory device.
Nonvolatile memory devices retain stored data even when power is interrupted. However, two-dimensional (2D) memory devices fabricated in a single layer on a silicon substrate have limitations in improving integration density. Therefore, 3D nonvolatile memory devices with memory cells stacked vertically from a silicon substrate are desirable.
Hereinafter, the structure and limitation of a conventional 3D nonvolatile memory device will be described in detail with reference to FIG. 1.
FIG. 1 is a cross-sectional view of a conventional 3D nonvolatile memory device. Specifically, FIG. 1 is a cross-sectional view of a nonvolatile memory device in which strings are vertically arranged over a substrate. For the sake of convenience, a description about a process of forming a lower selection transistor and an upper selection transistor is omitted.
Referring to FIG. 1, a plurality of interlayer insulating layers 11 and a plurality of gate electrode conductive layers 12 are alternately formed on a substrate 10 having required lower structures such as source lines and lower select transistors that are formed, for example, below the interlayer insulating layers 11 and the plurality of gate electrode conductive layers 12. Thereafter, the interlayer insulating layers 11 and the gate electrode conductive layers 12 are selectively etched to form a channel trench exposing the surface of the substrate 10.
A charge blocking layer, a charge trapping layer, and a tunnel insulating layer are sequentially formed over the resulting structure including the channel trench. Thereafter, an etch-back process is performed to expose the surface of the substrate 10. For illustration purposes, the charge blocking layer, the charge trapping layer, and the tunnel insulating layer are shown as one layer denoted by a reference numeral 13.
The channel trench is filled with a channel layer to form a channel 14 protruding vertically from the substrate 10. Herein, the channel layer may be formed by growing a monocrystalline silicon layer through an epitaxial growth process, or may be formed by depositing a polysilicon layer through a chemical vapor deposition (CVD) process.
Consequently, a plurality of stacked memory cells are formed along the channel 14 protruding vertically from the substrate 10, and the memory cells are connected in series between a lower select transistor (not shown) and an upper select transistor (not shown) to constitute one string.
However, the foregoing conventional method has limitations in controlling the doping concentration of the channel 14.
In general, for fabrication of a nonvolatile memory device, the doping concentration of the channel 14 is controlled to control the threshold voltage of the memory cells. For example, the threshold voltage is controlled by doping the channel layer with n-type impurities at a low concentration. In the case of a conventional planar nonvolatile memory device, a channel layer is formed and the channel layer is doped with impurities through an ion implantation process, thereby forming a channel with a low doping concentration.
However, in the case of the vertical channel type nonvolatile memory device, because the channel trench is filled with the channel layer to form the channel 14, doping by ion implantation is difficult to implement. Also, even when the channel layer is formed through a doping process, it is not easy to implement a doping concentration of less than 1E19 atoms/cm3. That is, according to the conventional method, it is impossible to form a vertical channel with a low doping concentration for fabrication of a 3D nonvolatile memory device.
For illustration purposes, limitations that occur in forming a channel of a memory cell have been explained. However, such limitations may also occur in forming a lower select transistor or an upper select transistor.